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IDT70T653M
High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table IV — Example of Semaphore Procurement Sequence (1,2,3)
Functions
No Action
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
D 0 - D 8 Left
D 18 - D 26 Left
1
0
0
1
1
0
1
1
1
0
1
D 0 - D 8 Right
D 18 - D 26 Right
1
1
1
0
0
1
1
0
1
1
1
Status
Semaphore free
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
5679 tbl 19
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70T653M.
2. There are eight semaphore flags written to via I/O 0 and read from I/Os (I/O 0 -I/O 8 and I/O 18 -I/O 26 ). These eight semaphores are addressed by A 0 - A 2 .
3. CE = V IH , SEM = V IL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Functional Description
The IDT70T653M provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70T653M has an automatic power down
feature controlled by CE . The CE 0 and CE 1 control the on-chip power
down circuitry that permits the respective port to go into a standby mode
when not selected ( CE = HIGH). When a port is enabled, access to the
entire memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
( INT L ) is asserted when the right port writes to memory location 7FFFE
(HEX), where a write is defined as CE R = R/ W R = V IL per the Truth Table.
The left port clears the interrupt through access of address location 7FFFE
when CE L = OE L = V IL , R/ W is a "don't care". Likewise, the right port
interrupt flag ( INT R ) is asserted when the left port writes to memory location
7FFFF (HEX) and to clear the interrupt flag ( INT R ), the right port must read
the memory location 7FFFF. The message (36 bits) at 7FFFE or 7FFFF
is user-defined since it is an addressable SRAM location. If the interrupt
function is not used, address locations 7FFFE and 7FFFF are not used
as mail boxes, but as part of the random access memory. Refer to Truth
Table III for the interrupt operation.
Busy Logic
The BUSY pin operates as a write inhibit input pin. Normal operation
can be programmed by tying the BUSY pins HIGH. If desired, unintended
write operations can be prevented to a port by tying the BUSY pin for that
port LOW.
Semaphores
The IDT70T653M is an extremely fast Dual-Port 512K x 36 CMOS
Static RAM with an additional 8 address locations dedicated to binary
18
semaphore flags. These flags allow either processor on the left or
right side of the Dual-Port RAM to claim a privilege over the other
processor for functions defined by the system designer’s software. As
an example, the semaphore can be used by one processor to inhibit
the other from accessing a portion of the Dual-Port RAM or any other
shared resource.
The Dual-Port RAM features a fast access time, with both ports being
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be read from
or written to at the same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphore location. Semaphores are protected against such ambiguous
situations and may be used by the system program to avoid any conflicts
in the non-semaphore portion of the Dual-Port RAM. These devices have
an automatic power-down feature controlled by CE 0 and CE 1 , the Dual-
Port RAM chip enables, and SEM , the semaphore enable. The CE 0 , CE 1 ,
and SEM pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
Systems which can best use the IDT70T653M contain multiple
processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These ystems can
benefit from a performance increase offered by the IDT70T653Ms
hardware semaphores, which provide a lockout mechanism without
requiring complex programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated invarying
configurations. The IDT70T653M does not use its semaphore flags to
control any resources through hardware, thus allowing the system
designer total flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speed systems.
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